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1 of 9 121906 features ? 5v or 3.3v power-on reset ? true 3v operatio n power switch ? switches to battery at 3.8v (2.6v for 3.3v versions) ? excellent for systems designed to operate with dual power supplies ? asserts resets durin g power transients ? maintains reset for 350ms after v cc returns to an in-toleran ce condition ? reduces need for di screte components ? precision temperature-compensated voltage reference and voltage sensor ? 8-pin dip or space saving 8-pin so surface mount available ? cmos reset output for low current operation ? operating temperature of -40 c to +85 c ? perfect for pic microp rocessor applications pin assignment ds1836a/c (*ds1836b/d) pin description v cc - power supply input v bat - battery supply input nc - no connect v out - power supply output gnd - ground in - sense input nmi - non-maskable interrupt rst (*rst) - reset output description the ds1836 micromanag er performs three vital system functio ns. first, a precisi on temperature- compensated reference and comparator circuit monitor th e status of th e voltage on v cc and when an out- of-tolerance condition is detected, an internal power-f ail signal is genera ted that forces th e reset active. if v cc continues to degrade, it switche s to the batter y supply when v cc drops below 3.8v (2.6v for 3.3v versions). when v cc exceeds 3.9v (2.8v for 3.3v versions); v out will again be supplied from v cc . reset will remain activ e for 350 ms after v cc returns to an in-tol erance condition. lastly, the ds1836 supports a sense input that sends a non-maskable interrupt wh enever the sense input drops below 1.25v. ds1836/a/b/c/d 3.3v/5v micromanage r www.maxim-ic.com 8-pin so (150mil) 1 2 3 4 8 7 6 5 v cc v bat nc v out rst(*rst) nmi in gnd 8-pin dip (300mil) v cc v bat nc v out rst(*rst) nmi in gnd 1 2 3 4 8 7 6 5
ds1836a/b/c/d 2 of 9 operation power monitor the ds1836 provides the functions of detecting out-of-tolerance conditions on a 3.3v or 5v power supply and warning a processor-based system of impending power failure. when v cc is detected as out of tolerance the rst will be forced active. when v cc returns to a vali d state the rst will remain active for about 350ms and then re turn to an inactive st ate until the next v cc out-of-tolerance condition. on power-up reset is kept active for approximately 350ms after the power supply input has reached the selected tolerance. this allows the power supply and system pow er to stabilize befo re rst is released. power switch (ds1836a & b) the ds1836 swit ches the v out output between v cc and v bat . on the initial power-up, v out draws current from the v bat input until v cc exceeds 3.9v. when v cc exceeds 3.9v v out switches from v bat to v cc and will not sw itch back to v bat until v cc drops below 3.8v. when v cc is below 3.8v, power will be drawn from the supply with th e highest voltag e: either v cc or v bat . power switch (ds1836c & d) the ds1836 swit ches the v out output between v cc and v bat . on the initia l power up, v out draws current from the v bat input until v cc exceeds 2.8v. when v cc exceeds 2.8v v out switches from v bat to v cc and will not sw itch back to v bat until v cc drops below 2.6v. when v cc is below 2.6v, power will be drawn from the supply with th e highest voltage either v cc or v bat . block diagram figure 1 * ds1836b and ds1836d
ds1836a/b/c/d 3 of 9 non-maskable interrupt the ds1836 generates a non -maskable interrupt ( nmi ) for early warnin g of a power fail ure. a precision comparator monitors the voltage leve l at the in pin relative to an on-chip reference generated by an internal band gap. the in pin is a high impedance input allowing for a user-defined sense point. an external resistor voltage divider network (figure 3) is used to interface with high voltage signals. this sense point may be derived fr om a regulated supply or from a higher dc voltage level closer to the main system power input. since the in trip point v tp is 1.25v, the proper values for r1 and r2 can be determined by the equation as shown in figu re 3. proper operation of the ds1836 requir es that the maximum voltage at the in pin be limited to the active supply (v cc or v bat ). therefore, the maximum allowable voltage at the supply being monitored (v max ) can also be derived as shown in fi gure 3. a simple approach to solving the equation is to se lect a value for r2 high enough to keep power consumption low and solve for r1. th e flexibility of the in input pin allows for detection of power loss at the earliest point in a power supply system, ma ximizing the amount of time for system shutdown between nmi and rst (or rst ). a pull-up resistor is required for proper operation of the nmi open-drain output. a 10k resistor would be a typical value for the pull-up resistor. typical application figure 2
ds1836a/b/c/d 4 of 9 non-maskable interr upt circuit example figure 3 v sense = r2 r2 r1 + x 1.25 example: v sense = 4.50v at the trip point 100k = r2 therefore: 4.5 = 100 k 100k r1 + timing diagram: non-maskable interrupt figure 4
ds1836a/b/c/d 5 of 9 output valid conditions the ds1836 can maintain valid outputs as long as one input rema ins above 1.2v. however, the rst outputs on the ds1836a (or c) use a push-pu ll output structure wh ich can maintain a valid output below 1.2v on an input. to sink current below 1.2v a resistor can be connected from rst to gnd (see figure 5). this arrangement will maintain a valid value on the rst outputs even if all s upply inputs are at 0v. during conditio ns when the rst is in the inactive or high stat e this arrangement will draw current through the pull do wn resistor. a valu e of about 100 k should be adequate to maintain a valid condition. the ds1836 nmi output requires a pull-up resistor on the output to maintain a valid out put. the value of the resistor is not critical in most cases but must be set low enough to pull the output to a high state. a common value used is 10k s (see figure 3). application diagram: rst valid to 0v v cc on the ds1836a or ds1836c figure 5 timing diagram: power-up figure 6
ds1836a/b/c/d 6 of 9 timing diagram: power-down figure 7 timing diagram: power switch figure 8
ds1836a/b/c/d 7 of 9 absolute maxi mum ratings* voltage on v cc or v bat pin relative to ground -0.5v to +7.0v voltage on any i/o pin relative to gr ound** -0.5v to v out + 0.5v operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature 260c for 10 seconds * this is a stress rating only and functional operatio n of the device at these or any other conditions above those indicated in the oper ation sections of this specification is not implied. expos ure to absolute maximum rating conditions for extended periods of time may affect reliability. **the voltage input on in can exceed v cc /v bat if the input current is less than 10ma. recommended dc operating co nditions (-40 c to +85 c) parameter symbol min typ max units notes supply voltage v cc 1.2 5.5 v 1 secondary supp ly voltage v bat 1.2 5.5 v 1
ds1836a/b/c/d 8 of 9 dc electrical characteristics (-40 c to +85 c; v cc = 1.2v to 5.5v) parameter symbol min typ max units notes output voltage @ -500 a v oh v cc -0.5 v cc -0.1 v 1 input leakage i il -1.0 +1.0 a 2 output current @ 2.4v i oh 350 a 3 output current @ 0.4v i ol +10 ma 3 operating current @ ? 5.5v in i cc 35 55 a 4 operating current @ ? 3.6v in i cc 30 50 a 5 supply output current i cc01 100 ma 6 supply output current i cc02 100 ma 7 supply output voltage (v cc ) v out v cc -0.5 v cc -0.3 v 1, 8 supply output voltage (v bat ) v out v bat -0.5 v bat -0.3 v 1, 9 rst v cc trip point ds1836a(or b)-05 v cctp 4.50 4.63 4.75 v 1 rst v cc trip point ds1836a(or b)-10 v cctp 4.25 4.37 4.50 v 1 rst v cc trip point ds1836c(or d)-10 v cctp 2.80 2.88 2.97 v 1 rst v cc trip point ds1836c(or d)-20 v cctp 2.67 2.72 2.80 v 1 power supply tr ip points (v cc to v bat ) ds1836 c or d v ccftp 2.60 2.65 2.70 v 1, 10 power supply tr ip points (v bat to v cc ) ds1836 c or d v ccrtp 2.70 2.75 2.80 v 1, 10 v bat leakage current i cc03 0.10 a 11 power supply tr ip points (v cc to v bat ) ds1836 a or b v ccftp 3.80 3.85 3.9 v 1, 10 power supply tr ip points (v bat to v cc ) ds1836 a or b v ccrtp 3.90 3.95 4.0 v 1, 10 in input trip point v tp 1.15 1.25 1.35 v 1 output capacitance c out 10 pf
ds1836a/b/c/d 9 of 9 a c electrical characteristics (-40 c to +85 c; v cc = 1.2v to 5.5v) parameter symbol min typ max units notes v tp to nmi delay t ipd 1 s reset active time t rst 200 350 500 ms v cc slew rate (v intp(min) to v intp(max) ) t r 0 ns v cc detect to rst t rpu 200 350 500 ms 12 v cc slew rate (v intp(max) to v intp(min) ) t f 300 s v cc detect to rst t rpd 2 10 s v cc to v bat (v cc falling through 2.6v) t fsw 1 s v bat to v cc (v cc rising through 2.8v) t rsw 1 s notes: 1) all voltages are refe renced to ground. 2) measured with outputs open an d inputs at v cc or gnd. 3) measured with ou tputs open and v cc or v bat < 2.7v. 4) measured with out puts open and both v cc and v bat < 5.5v. 5) measured with out puts open and both v cc and v bat < 3.6v. 6) v out = v cc - 0.3v. 7) v out = v bat - 0.3v. 8) v cc < 2.7v. 9) v bat < 2.0v and v cc < 1.9v. 10) v ccftp is offset by approximately 0.1v from v ccrtp . 11) v bat in the off state and v bat < v cc (v bat > v cc and v bat in the off state 1.5 a maximum). 12) t r = 5 s with one s upply < 2.5v. revision history pages changed at rev 1: 1, 9, 10
english ? ???? ? ??? ? ??? what's new products solutions design appnotes support buy company members ds1836c part number table notes: see the ds1836c quickview data sheet for further information on this product family or download the ds1836c full data sheet (pdf, 172kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 4. * some packages have variations, listed on the drawing. "pkgcode/variation" tells which variation the product uses. 5. part number notes free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds1836c-20+ pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8+7 * -40c to +85c rohs/lead-free: yes materials analysis ds1836c-10+ pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8+7 * -40c to +85c rohs/lead-free: yes materials analysis ds1836c-10 3.3v- 10% monitor pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8-7 * -40c to +85c rohs/lead-free: no materials analysis ds1836c-20 3.3v- 20% monitor pdip;8 pin;300 dwg: 56-g5005-000a (pdf) use pkgcode/variation: p8-7 * -40c to +85c rohs/lead-free: no materials analysis
ds1836cs-10+ soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * -40c to +85c rohs/lead-free: yes materials analysis ds1836cs-10-w 3.3v- 10% waiver soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * -40c to +85c rohs/lead-free: no materials analysis ds1836cs-20+ soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+5 * -40c to +85c rohs/lead-free: yes materials analysis ds1836cs-20+t&r 3.3v- 20% soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+5 * -40c to +85c rohs/lead-free: yes materials analysis ds1836cs-20/t&r 3.3v- 20% soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-5 * -40c to +85c rohs/lead-free: no materials analysis ds1836cs-20 3.3v- 20% monitor soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-5 * -40c to +85c rohs/lead-free: no materials analysis ds1836cs-10/t&r 3.3v- 10% soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * -40c to +85c rohs/lead-free: no materials analysis ds1836cs-10 3.3v- 10% monitor soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * -40c to +85c rohs/lead-free: no materials analysis ds1836cs-10+t&r 3.3v- 10% soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+5 * -40c to +85c rohs/lead-free: yes materials analysis didn't find what you need? contact us: send us an email copyright 2007 by maxim integrated products, dallas semiconductor ? legal notices ? privacy policy

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